Storage capacities of semiconductor memory devices continue to increase while dies on which the memory devices are fabricated continue to decrease. As a result, the number of memory cells present in memory devices and the complexity of the memory devices continues to increase as well. Additional memory cells and complexity require additional sense amplifiers, charge supply circuitry, addressing mechanisms, decoders, and the like. Further, the dimensions of components and/or structures present in memory devices shrink in response to the additional storage capacity. As a consequence, memory cells of memory devices can be more sensitive to defects, residues, and contaminants than memory cells of prior, smaller storage capacity memory devices. Such defects and contaminants can cause memory cells to be inoperable and unusable.
One technique to mitigate defects and contaminants and reduce the number of resulting defective cells is by tighter semiconductor fabrication process control and layout design/architecture. However, the ever-shrinking dimensions and increase in storage capacity can counteract the benefits of tighter process control and improvements in layout design/architecture. As a result, a significant number of memory devices are fabricated that include one or more defective memory cells. Without some type of correction mechanism, such memory devices can be unusable and/or introduce errors by their use.
One type of correction mechanism is to fabricate a number of redundant rows for memory devices. The number of redundant rows are formed in addition to original rows of memory cells. Then, during testing faulty memory cells and associated rows are identified. Subsequently, a selection device such as a fuse based device is employed to allow redundant rows to replace identified defective rows. As a result, addressing to memory cells in the original rows is rerouted to the replacement, redundant rows of memory cells. Thus, defective memory cells/rows are not apparent to external devices.
Another type of correction mechanism is to fabricate a number of redundant columns for memory devices in addition to original columns of memory cells. Defective or faulty memory cells/columns are then identified during testing. Subsequently, associated columns are replaced by one or more of the redundant columns by utilizing a selection mechanism such as a fuse based device. Accordingly, addressing to memory cells located in defective/faulty columns is rerouted to assigned redundant columns of memory cell. These defective memory cells/columns are not known to external devices.
One problem with the above correction mechanisms, redundant row replace and redundant column replace, is that large numbers of non-faulty cells can be needlessly replaced. For example, a single faulty memory cell, under a redundant row mechanism, requires that the row containing the single faulty memory cell be replaced. A single row in a memory device can have a large number of memory cells present, such as 512 or 1024 memory cells. Thus, one faulty memory cell can cause the other cells in the row, such as 511 or 1023, to be replaced. Such inefficiencies can reduce the storage capacity of memory devices by consuming valuable space on dies in order to provide for redundant rows and/or columns.